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| ? semiconductor components industries, llc, 2012 may, 2012 ? rev. 11 1 publication order number: ncp1605/d ncp1605, NCP1605A, ncp1605b enhanced, high voltage and efficient standby mode, power factor controller the ncp1605 is a controller that exhibits near ? unity power factor while operating in fixed frequency, discontinuous conduction mode (dcm) or in critical conduction mode (crm). housed in a soic ? 16 package, the circuit incorporates all the features necessary for building robust and compact pfc stages, with a minimum of external components. in addition, it integrates the skip cycle capability to lower the standby losses to a minimum. general features ? near ? unity power factor ? fixed frequency, discontinuous conduction mode operation ? critical conduction mode achievable in most stressful conditions ? lossless high voltage current source for startup ? soft skip cycle for low power standby mode ? switching frequency up to 250 khz ? synchronization capability ? fast line / load transient compensation ? valley turn on ? high drive capability: ? 500 ma / +800 ma ? signal to indicate that the pfc is ready for operation (?pfcok? pin) ? v cc range: from 10 v to 20 v ? follower boost operation ? two v cc turn ? on threshold options: 15 v for ncp1605 & ncp1605b; 10.5 v for NCP1605A ? these devices are pb ? free, halogen free/bfr free and are rohs compliant safety features ? output under and overvoltage protection ? brown ? out detection ? soft ? start for smooth startup operation ? overcurrent limitation ? zero current detection protecting the pfc stage from inrush currents ? thermal shutdown ? latched off capability typical applications ? pc power supplies ? all off line appliances requiring power factor correction http://onsemi.com soic ? 16 d suffix case 751b device package shipping ? ordering information marking diagrams x = a or b a = assembly location wl = wafer lot y = year ww = work week g = pb ? free package 1 ncp1605g awlyww 1 2 3 4 5 6 7 8 16 15 14 12 11 10 9 (top view ) cs in stby bo v control fb cs out /zcd ct osc/sync hv nc pfcok/ref5v v cc gnd ovp/uvp drv 13 stdwn pin connections ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. 1 ncp1605dr2g soic ? 16 (pb ? free) 2500/t ape & reel 16 NCP1605Adr2g soic ? 16 (pb ? free) 2500/t ape & reel ncp1605xg awlyww 1 16 ncp1605bdr2g soic ? 16 (pb ? free) 2500/t ape & reel
ncp1605, NCP1605A, ncp1605b http://onsemi.com 2 emi filter ac line load l1 d1 rcs m1 cbo 1 2 3 4 13 16 14 15 5 6 7 89 12 10 11 ct pfcok stby control fb ovp rzcd rdrv c in r ocp r bo2 r bo1 + v out + v cc cv cc i coil v in c bulk v cc v out c osc r ovp1 r ovp2 r out1 cv ref cv ctrl r out2 i coil figure 1. maximum ratings pin rating symbol value unit 11 power supply input v cc ? 0.3, +20 v 11 maximum transient v oltage (note 1) v cc ? 0.3, +25 v 1, 2, 4, 5, 6, 7, 8, 13 and 14 input v oltage v i ? 0.3, +9 v 6 maximum current i csout /zcd ? 3, 10 ma 3 v control pin v control ? 0.3, v control max (note 2) v 16 high voltage pin v hv ? 0.3, 600 v v power dissipation and thermal characteristics: maximum power dissipation @ t a = 70 c thermal resistance junction ? to ? air p d r ja 550 145 mw c/w operating junction temperature range t j ? 40, +125 c maximum junction t emperature t jmax 150 c storage temperature range t smax ? 65 to 150 c lead temperature (soldering, 10 s) t lmax 300 c esd capability, hbm model (all pins except hv) (note 3) hbm 2000 v esd capability, mm model (all pins except hv) (note 3) mm 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the maximum transient voltage with a corresponding maximum transient current at 100 ma. the maximum transient power handling capability must be observed as well. 2. ?v control max? is the pin clamp voltage. 3. this device series contains esd protection rated using the following tests: human body model (hbm) 2000v per jedec standard jesd22, method a1 14e. machine model (mm) 200v per jedec standard jesd22, method a1 15a. 4. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78. ncp1605, NCP1605A, ncp1605b http://onsemi.com 3 typical electrical characteristics (conditions: v cc = 16 v, v hv = 50 v, v pin2 = 2 v, v pin13 = 0 v, t j from 0 c to +125 c, unless otherwise specified) (note 2) symbol rating min typ max unit gate drive section t rise output voltage rise time @ c l = 1 nf, from 1 v to 10 v ? 40 ? ns t fall output voltage fall time @ c l = 1 nf, from 10 v to 1 v ? 20 ? ns r oh source resistance @ i pin10 = 100 ma ? 15 25 i source source current capability (@ v pin10 = 0 v) ? 500 ? ma r ol sink resistance @ i pin10 = 100 ma ? 7 15 i sink sink current capability (@ v pin10 = 10 v) ? 800 ? ma regulation block v ref voltage reference ncp1605/a ncp1605b 2.425 2.430 2.500 2.500 2.575 2.550 v i ea error amplifier current capability ? 20 ? a g ea error amplifier gain 100 200 300 s ib pin4 pin 4 bias current @ v pin4 = v ref ? 500 ? 500 na v control ? v control max ? v control min ? v control l pin 2 v oltage: ? @ v pin4 = 2 v ? @ v pin4 = 3 v ? ? 2.7 3.6 0.6 3.0 ? ? 3.3 v v out l / v ref ratio (v out low detect threshold / v ref ) (note 6) 95.0 95.5 96.0 % h out l / v ref ratio (v out low detect hysteresis / v ref ) (note 6) ? ? 0.5 % i boost pin 2 source current when (v out low detect) is activated 190 240 290 a shutdown block i leakage current sourced by pin 13 @ v pin14 = 2.3 v ? 500 ? 500 na v stdwn pin 13 threshold for shutdown 2.375 2.500 2.625 v over and under voltage protections v ovp overvoltage protection threshold 2.425 2.500 2.575 v v ovp / v ref ratio (v ovp / v ref ) (note 5) 99.5 100.0 100.5 % v uvp / v ref ratio uvp threshold over v ref 8 12 16 % ib pin14 pin 13 bias current: @ v pin14 = v ovp @ v pin14 = v uvp ? 500 ? 500 ? ? 500 500 na ramp control i ramp ? 1.00 v i ramp ? 1.75 v i ramp ? 2.50 v pin 7 source current: @ v pin4 = 1.00 v @ v pin4 = 1.75 v @ v pin4 = 2.50 v 54 156 313 60 182 370 69 214 428 a vcl_ff pin 7 clamp voltage @ v pin4 = v pin2 = 2 v and v pin6 = 0 v ? 5 ? v v cl crm pin 7 clamp voltage @ v pin4 = 0 v, v pin2 = 2 v and v pin6 = 1 v 0.9 1 1.1 v r ct ratio (pin 7 clamp voltage / (pin 7 charge current) (v cl crm / i ramp ) @ v pin6 = 0 v and ? v pin4 = 1.00 v ? v pin4 = 1.75 v ? v pin4 = 2.50 v ? ? ? 16.7 5.4 2.7 ? ? ? k t on min delay (v pin7 > 5 v) to (drv low) ? 90 200 ns 5. not tested; guaranteed by characterization 6. not tested; guaranteed by design ncp1605, NCP1605A, ncp1605b http://onsemi.com 4 typical electrical characteristics (conditions: v cc = 16 v, v hv = 50 v, v pin2 = 2 v, v pin13 = 0 v, t j from 0 c to +125 c, unless otherwise specified) (note 2) symbol unit max typ min rating c int average pin 7 internal capacitance (v pin7 varying from 0 and 1 v) guaranteed by design ? 15 25 pf v init maximum pin 7 voltage allowing the setting of the pwm latch ? 50 90 mv i ramp_sink pin 7 sink current (drive low) @ v pin7 = 1 v ? 10 ? ma current sense block off100 current sense pin voltage, ncp1605/a 100 a being drawn from pin 5 ncp1605b ? 20 ? 5.0 6.0 6.0 20 15 mv off10 current sense pin voltage, 10 a being drawn from pin 5 3.0 8.0 13 mv i max overcurrent protection threshold 230 250 265 a t ocp (ipin5 > 250 a) to (drv low) propagation delay (note 5) ? 100 200 ns k cs10 ratio (i pin6 /i pin5 ) @ i pin5 = 10 a 99 108 117 % k cs200 ratio (i pin6 /i pin5 ) @ i pin5 = 200 a 98 101 103 % v zcd pin 6 comparator threshold 50 100 200 mv t zcd delay from (v pin6 < v zcd ) to (drv high) ? 120 240 ns standby input v stby standby mode threshold (v pin1 falling) 280 310 340 mv h stby hysteresis for standby mode detection 25 30 50 mv v skip out / v out l ratio (pin 4 voltage to terminate a skip period) over the (v out low detect threshold) (note 6) 99 100 101 % oscillator / synchronization block i charge oscillator charge current 90 100 110 a i disch oscillator discharge current 90 100 110 a v sync_h comparator upper threshold ? 3.0 ? v v sync_l comparator lower threshold ? 2.0 ? v swing comparator swing (v sync_h ? v sync_l ) 0.9 1.0 1.1 v t sync_min minimum synchronization pulse width for detection ? ? 500 ns pfcok / ref5v v pfcok l pin 12 voltage @ v pin13 = 5 v, 250 a being sunk by pin 12 ? 60 120 mv v pfcok h (pin 12 voltage @ v pin13 = 0 v and ncp1605/a v pin3 = 5 v, with a 250 a sourced by pin 12) ncp1605b (pin 12 voltage @ v pin13 = 0 v and ncp1605/a v pin3 = 5 v, with a 5 ma sourced by pin 12) ncp1605b 4.7 4.75 4.5 4.5 5.0 5.0 5.0 4.72 5.3 5.3 5.3 5.0 v icap_ref current capability 5 .0 10 ? ma brown ? out detection block v boh brown ? out comparator threshold (v pin2 rising) ncp1605/a ncp1605b 0.9 0.93 1.0 1.0 1.1 1.07 v v bol brown ? out comparator threshold (v pin2 falling) ncp1605/a ncp1605b 0.45 0.465 0.50 0.50 0.55 0.535 v ib bo pin 2 bias current @ v pin2 = 0.5 v and 1 v ? 500 ? 500 na thermal shutdown t limit thermal shutdown threshold ? 155 ? c h temp thermal shutdown hysteresis ? 15 ? c 5. not tested; guaranteed by characterization 6. not tested; guaranteed by design ncp1605, NCP1605A, ncp1605b http://onsemi.com 5 typical electrical characteristics (conditions: v cc = 16 v, v hv = 50 v, v pin2 = 2 v, v pin13 = 0 v, t j from 0 c to +125 c, unless otherwise specified) (note 2) symbol unit max typ min rating v cc undervoltage lockout section v cc on turn on threshold level, v cc raising up ncp1605 NCP1605A ncp1605b 14 9.5 14.2 15 10.5 15 16 11.5 15.55 v v cc off minimum operating voltage after turn ? on ncp1605/a ncp1605b 8.0 8.6 9.0 9.0 10 9.35 v h uvlo difference (v cc on ? v cc off) ncp1605/b NCP1605A 5.0 1.2 6.0 1.5 ? ? v v cc stup v cc threshold below which the startup current source turns on 5.5 7.0 8.0 v h latchoff difference (v cc off ? v cc stup) 0.6 2.0 ? v v cc rst v cc level at which the logic resets 2.0 4.0 5.0 v v cc inhibit threshold which ic2 stops working & switches to ic1 ncp1605/a i c2 = 1 ma ncp1605b ? 0.3 1.25 1.25 ? 2.2 v internal startup current source ic1_hv (high ? voltage current source ncp1605/a sunk by pin 16, v cc = 13.5 v) ncp1605b 5.0 7.0 12 12 20 17 ma ic1_vcc (startup charge current flowing ncp1605/a out of the v cc pin, v cc = 13.5 v) ncp1605b 5.0 6.5 12 12 20 16.5 ma ic2 high ? voltage current source, v cc = 0 v ncp1605/a ncp1605b ? 0.375 0.5 0.5 1.0 0.87 ma device consumption i cc_op1 i cc_op2 i cc_off i cc_latchoff power supply current: operating (@ v cc = 16 v, no load, no switching) operating (@ v cc = 16 v, no load, switching) off mode (@ v cc = 16 v, pin 2 grounded) latched ? off mode (@ v cc = 13.5 v and v pin13 = 5 v) ? 2.0 310 310 2.5 3.5 570 550 5.0 7.0 780 750 ma ma a a 5. not tested; guaranteed by characterization 6. not tested; guaranteed by design ncp1605, NCP1605A, ncp1605b http://onsemi.com 6 pin function description pin number name function 1 stby an external signal (typically, a portion of the feedback signal of the downstream converter or a filtered portion of the smps drive pulses) should be applied to pin 1. when the pin 3 voltage goes below 300 mv, the circuit enters a burst mode operation where the bulk voltage varies between the regulation voltage and 95.5% of this level. 2 brown ? out / inhibition apply a portion of the averaged input voltage to detect brown ? out conditions. if v pin2 is lower than 0.5 v, the circuit stops pulsing until v pin2 exceeds 1 v (0.5 v hysteresis). ground pin 6 to disable the part. 3 v control / soft ? start the error amplifier output is available on this pin. the capacitor connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 hz to achieve high power factor ratios. pin 3 is grounded when the circuit is off so that when it starts operation, the power increases slowly (soft ? start). 4 feedback this pin receives a portion of the pre ? converter output voltage. this information is used for the regulation and the ?output low? detection (v out l) that drastically speed up the loop response when the output voltage drops below 95.5% of the wished level. 5 current sense input this pin monitors a negative voltage proportional to the coil current. this signal is sensed to limit the maximum coil current and detect the core reset (coil demagnetization). 6 current sense output this pin sources the pin 5 current. place a resistor between pin 6 and ground to build the voltage proportional to the coil current and detect the core reset. the impedance between pin 6 and ground should not exceed 3 times that of the pin 5 to ground. you can further apply the voltage from an auxiliary winding to improve the valley detection of the mosfet drain source voltage. 7 ct (ramp) the circuit controls the power switch on ? time by comparing the pin 7 ramp to an internal voltage (?v ton ?) derived from the regulation block and the sensed ?dcycle? (relative duration of the current cycle over the corresponding switching period). pin 7 sources a current proportional to the squared output voltage to allow the follower boost operation (optional) where the pfc output voltage stabilizes at a level that varies linearly versus the ac line amplitude. this technique reduces the difference between the output and input voltages, to optimize the boost efficiency and minimize the size and cost of the pfc stage 8 oscillator / synchronization connect a capacitor or apply a synchronization signal to this pin to set the switching frequency. if the coil current cycle is longer than the selected switching period, the circuit delays the next cycle until the core is reset. hence, the pfc stage can operate in crm in the most stressful conditions. 9 gnd connect this pin to the pre ? converter ground. 10 drive the high current capability of the totem pole gate drive (+0.5/ ? 0.8 a) makes it suitable to ef fectively drive high gate charge power mosfets. 11 v cc this pin is the positive supply of the ic. the circuit starts to operate when v cc exceeds 15 v (10.5 v for NCP1605A) and turns off when v cc goes below 9 v (typical values). after startup, the operating range is 10 v up to 20 v. 12 pfcok / ref5v the pin 12 voltage is high (5 v) when the pfc stage is in a normal, steady state situation and low otherwise. this signal serves to ?inform? the downstream converter that the pfc stage is ready and that hence, it can start operation. 13 stdwn apply a voltage higher than 2.5 v on pin 13 to permanently shutdown the circuit. this pin can be used to monitor the voltage across a thermistor in order to protect the application from an excessive heating and/or to detect an overvoltage condition. to resume operation, it is necessary to decrease the circuit v cc below v cc rst (4 v typically) by for instance, unplugging the pfc stage and replugging it after v cc is discharged. 14 ovp / uvp the circuit turns off when v pin14 goes below 300 mv (uvp) and disables the drive as long as the pin voltage exceeds 2.5 v (ovp). 15 nc creepage distance. 16 hv connect pin 16 to the bulk capacitor. the internal startup current source placed between pin 16 and the v cc terminal, charges the v cc capacitor at startup. ncp1605, NCP1605A, ncp1605b http://onsemi.com 7 2.41 2.43 2.45 2.47 2.49 2.51 2.53 2.55 2.57 2.59 v ref , (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 2. reference v oltage vs. temperature 235 240 245 250 255 260 265 ? 40 ? 15 10 35 60 85 110 i ref , ( a) t j , junction temperature ( c) figure 3. reference current v s. temperature 2.40 2.44 2.48 2.52 2.56 2.60 figure 4. overvoltage threshold vs. temperature v ovp , (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 97 98 99 100 101 102 103 figure 5. ratio overvoltage threshold overvoltage reference vs. temperature v ovp /v ref , (%) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 2.36 2.41 2.46 2.51 2.56 2.61 v stdwn , (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 6. shutdown threshold vs. temperature ncp1605, NCP1605A, ncp1605b http://onsemi.com 8 0 0.1 0.2 0.3 0.4 0.5 0.6 v uvp , (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 7. undervoltage protection threshold vs. temperature 7 9.04 11.08 13.12 15.16 v uvp v ref , (%) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 8. ratio (v uvp /v ref ) vs. temperature 13.9 14.2 14.5 14.8 15.1 15.4 vcc on , (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 9. v cc turn on threshold vs. temperature (v cc raising up) ? ncp1605/b 7.9 8.2 8.5 8.8 9.1 9.4 9.7 vcc off , (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 10. v cc minimum operating voltage after turn on ? ncp1605/b 5.2 5.5 5.8 6.1 6.4 6.7 h uvlo , (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 11. difference (vcc on ? vcc off ) vs. temperature ? ncp1605/b 4.8 5.3 5.8 6.3 6.8 7.3 7.8 8.3 8.8 v cc stup, (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 12. v cc threshold below which the startup current source turns on vs. temperature ncp1605, NCP1605A, ncp1605b http://onsemi.com 9 0.5 1 1.5 2 2.5 3 3.5 4 figure 13. difference (v cc off ? v cc stup) vs. temperature h latchoff , (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 0 1 2 3 4 5 6 vcc rst , (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 14. v cc level below which the logic resets vs. temperature 4 6 8 10 12 14 16 18 20 ic1_hv, (ma) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 15. high ? voltage current source (sunk by pin 16) vs. temperature (@ v cc = 13.5 v) 4 6 8 10 12 14 16 18 20 figure 16. startup charge current flowing out of the v cc pin vs. temperature (@ v cc = 13.5 v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 ic1_v off , (ma) 0 0.3 0.6 0.9 1.2 figure 17. high ? voltage current source vs. temperature (@ v cc = 0 v) ic2, (ma) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 0 10 20 30 40 50 60 70 80 90 hv_leakage, ( a) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 18. pin 16 leakage current vs. temperature (@ v pin16 = 500 v and v cc = 16 v) ncp1605, NCP1605A, ncp1605b http://onsemi.com 10 12 14 16 18 20 22 24 iea_source, ( a) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 19. source current capability of the error amplifier vs. temperature ? 24 ? 22 ? 20 ? 18 ? 16 ? 14 ? 12 iea_sink, ( a) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 20. sink current capability of the error amplifier vs. temperature 60 100 140 180 220 260 300 gea, ( s) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 21. error ampli fier gain vs. temperature ? 150 ? 100 ? 50 0 50 100 150 ib pin4 , (na) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 22. feedback pin bias current vs. temperature (@ v pin4 = v ref ) 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 figure 23. v control maximum voltage vs. temperature v control max, (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 (v control ), (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 24. v control maximum swing ( v control ) vs. temperature ncp1605, NCP1605A, ncp1605b http://onsemi.com 11 95.1 95.2 95.3 95.4 95.5 95.6 95.7 95.8 95.9 v out l/v ref , (%) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 25. ratio (v out low detect threshold) / v ref vs. temperature 190 200 210 220 230 240 250 260 270 i boost , ( a) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 26. pin 3 source current when (v out low detect threshold) is activated vs. temperature 80 90 100 110 figure 27. oscillator charge current vs. temperature i charge , ( a) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 80 90 100 110 i disch , ( a) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 28. oscillator discharge current vs. temperature 0.91 0.93 0.95 0.97 0.99 1.01 swing, (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 29. oscillator swing vs. temperature 0 25 50 75 100 125 150 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 pfcok_l (mv) figure 30. pfcok pin low level voltage vs. temperature 85 95 105 85 95 105 ncp1605, NCP1605A, ncp1605b http://onsemi.com 12 4.5 4.7 4.9 5.1 5.3 5.5 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 pfcok_h, (v) figure 31. pfcok pin high level voltage vs. temperature (250 a load) 0 1 2 3 4 5 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 i cc _op1, (ma) figure 32. operating consumption vs. temperature (v cc = 16 v, no load, no switching) 1 2 3 4 5 6 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 i cc _op2, (ma) figure 33. operating consumption vs. temperature (v cc = 16 v, no load, switching) 300 400 500 600 700 800 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 i cc off, ( a) figure 34. off mode consumption vs. temperature (v cc = 16 v, pin 2 grounded) 300 400 500 600 700 800 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 i cc stdown, ( a) figure 35. shutdown mode consumption vs. temperature (v cc = 16 v, pin 2 gnd) ncp1605, NCP1605A, ncp1605b http://onsemi.com 13 0.9 0.95 1 1.05 1.1 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 v cbo h, (v) figure 36. brown ? out upper threshold vs. temperature 0.4 0.45 0.5 0.55 0.6 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 v cbo l, (v) figure 37. brown ? out lower threshold vs. temperature ? 2 0 2 4 6 8 10 12 14 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 off100, (mv) figure 38. current sense pin voltage vs. temperature (100 a being drawn from pin 5) 2 4 6 8 10 12 14 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 off10, (mv) figure 39. current sense pin voltage vs. temperature (10 a being drawn from pin 5) 52 54 56 58 60 62 64 66 68 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 i ramp _1.00 v, ( a) figure 40. pin 7 source current @ v pin4 = 1.0 v vs. temperature 158 168 178 188 198 208 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 i ramp _1.75 v, ( a) figure 41. pin 7 source current @ v pin4 = 1.75 v vs. temperature 163 173 183 193 203 ncp1605, NCP1605A, ncp1605b http://onsemi.com 14 325 335 345 365 375 385 405 415 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 i ramp _2.50 v, ( a) figure 42. pin 7 source current @ v pin4 = 2.5 v vs. temperature 3 4 5 6 7 8 figure 43. ratio pin 7 clamp voltage / (pin 7 charge current) that is (v clcrm / i ramp ) @ v pin6 = 0 v and v pin4 = 1.75 v t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 r ct (k ) 104 106 108 110 112 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 t zcd , (ns) figure 44. ratio (i pin6 / i pin5 ) @ i pin5 = 10 a vs. temperature 40 60 80 100 120 140 160 180 200 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 v zcd , (mv) figure 45. pin 6 comparator threshold vs. temperature 40 60 80 100 120 140 160 180 200 220 t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 kcs10, (%) figure 46. delay from (zcd pin low) to (drv high) vs. temperature 260 280 300 320 340 v skip h, (v) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 47. skip cycle threshold (v pin1 falling) vs. temperature 270 290 310 330 355 395 ncp1605, NCP1605A, ncp1605b http://onsemi.com 15 0 20 40 60 80 100 120 140 160 180 t o min, (ns) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 48. minimum on ? time vs. temperature 8 10 12 14 16 18 20 22 24 26 r oh , ( ) t j , junction temperature ( c) ? 40 ? 15 10 35 60 85 110 figure 49. gate drive source resistance vs. temperature 2 4 6 8 10 12 14 16 r ol , ( ) ? 40 ? 15 10 35 60 85 110 t j , junction temperature ( c) figure 50. gate drive sink resista nce vs. temperature ncp1605, NCP1605A, ncp1605b http://onsemi.com 16 1 v / 0.5 v drv regul uvlos latch reset hv output buffer bo_nok fb ct pwm latch s q r pwm comparator vton processing circuitry outon stdwn gnd r csin ics ics > 250 a ocp dead ? time detection latch s q r outon dt off r ocp off skip r skip pfcok / oscillator / synchronization block osc / dt ct_ok outon ovp vcc ncp1605, NCP1605A, ncp1605b http://onsemi.com 18 ncp1605(a) operation modes like the ncp1601, the ncp1605: ? features a current sense block that prevents the pfc stage from operating in ccm: as long as the coil current is not null, the power switch is not allowed to turn on. hence the circuit can only operate in either fixed frequency dcm or crm. ? features the capability to exhibit near ? unity power factor while operating in any type of discontinuous conduction mode operation: dcm or crm. ? auto adapts: if there is some current flowing through the coil when the clock occurs to initiate a new current cycle, the pfc stage enters crm. on the other hand, if the clock occurs during dead ? times, one obtains a fixed frequency operation dcm. thanks to its special oscillator/synchronization arrangement, the circuit automatically enters the appropriate mode crm or dcm. it is worth noting that jumps between the crm and modes cause absolutely no degradation: the input current keeps being properly shaped and there is no discontinuity in the power transfer. given the dead ? time presence, dcm needs a higher peak inductor current compared to crm for the same delivered power. hence, the coil is generally designed to have crm at the most stressful conditions while dcm limits the switching frequency at lower load. the circuit can also transition within an ac line cycle so that: ? crm reduces the current stress around the sinusoid top. ? dcm limits the frequency around the line zero crossing. this capability offers the best of each mode without the drawbacks. the way the circuit modulates the mosfet on ? time allows this facility. figure 52. dcm and crm operation within a sinusoid cycle the ncp1605(a) can jump from dcm to crm within a sinusoid cycle (and vice versa) without any discontinuity in the current shaping or the power transfer. inductor current, i l current time dcm critical mode dcm input current, i in ncp1605 on ? time modulation let?s study the ac line current absorbed by the pfc boost. the initial inductor current of each switching cycle is always zero. the coil current ramps up when the mosfet is on . the slope is (v in /l) where l is the coil inductance. at the end of the on ? time (t1), the coil demagnetization phase starts. the coil current ramps down until this sequence ends when it reaches zero. the duration of this phase is (t2). the system enters then the dead ? time (t3) that lasts until the next clock is generated. one can show (refer to ncp1601 data sheet) that the ac line current is given by: i in v in t 1 (t 1 t 2 ) 2tl (eq. 1) where t = (t1 + t2 + t3) is the switching period and v in is the ac line rectified voltage. to the light of this equation, we immediately note that i in is proportional to v in if [t1(t1 + t2)/t] is a constant. ncp1605, NCP1605A, ncp1605b http://onsemi.com 19 figure 53. pfc boost converter figure 54. inductor current in dcm l i in v in v out time inductor current i pk t t 1 t 2 t 3 the ncp1605 operates in voltage mode. as portrayed by figure 55, the mosfet on time t 1 is controlled by the signal v ton generated by the regulation block and the pin 4 ramp as follows: t 1 c pin7 v ton i pin7 (eq. 2) the charge current that is sourced by pin 7 [i pin7 = 60 a/v 2 * (v pin4 ) 2 ] is constant at a given input voltage (v pin4 is proportional to the output voltage). c pin7 that is the capacitor connected between pin 7 and ground is also a constant. hence, the power factor correction is achieved when the v ton (t 1 + t 2 )/t term is constant. the output of the regulation block (v control ) is linearly changed into a signal (v regul ) varying between 0 and 1 v. (v regul ) is the voltage that is injected into the pwm section to modulate the mosfet duty ? cycle. however, like the ncp1601, the ncp1605 inserts some circuitry that processes (v regul ) to form the signal (v ton ) that is used in the pwm section instead of (v regul ) (see figure 56). (v ton ) is modulated in response to the dead ? time sensed during the precedent current cycles, that is, for a proper shaping of the ac line current (refer to ncp1601 data sheet). this modulation leads to: v ton t v regul t 1 t 2 or : v ton t 1 t 2 t v regul (eq. 3) given the regulation low bandwidth of the pfc systems, (v control ) and then (v regul ) are slow varying signals. hence, the (v ton * (t 1 + t 2 )/t) term is substantially constant. provided that in addition, (t1) is proportional to (v ton ), equation (1) leads to: (i in = k * v in ), where k is a constant. more exactly: i in k v in (eq. 4) where : k constant c pin7 v regul 120 l (v pin2 ) 2 the input current is then proportional to the input voltage. hence, the ac line current is properly shaped. one can note that this analysis is also valid in the crm case. this condition is just a particular case of this functioning where (t 3 = 0), which leads to (t 1 + t 2 = t) and (v ton = v regul ). that is why the ncp1605 automatically adapts to the conditions and jumps from dcm and crm (and vice versa) without power factor degradation and without discontinuity in the power delivery. remark: like in the ncp1601, the ?v ton processing circuit? is ?informed? when there is an ovp condition, not to over ? dimension v ton in that conditions. otherwise, an ovp sequence would be viewed as a dead ? time phase by the circuit and v ton would inappropriately increase to compensate it. similarly, the ?v ton processing circuit? is inhibited for a skip sequence not to over ? dimension ?v ton ? in this case (refer to figure 56). figure 55. pwm circuit and timing diagram figure 56. v ton processing circuit + ? ? > vton during (t1+t2) ? > 0 v during t3 (dead ? time) ? > vton*(t1+t2)/t in average + ? timing capacitor saw ? tooth to pwm latch pwm comparator in1 s1 s2 c1 r1 skip ovp oa1 off s3 dt (high during dead ? time) the integrator oa1 amplifies the error between v regul and in1 so that in average, (v ton *(t1+t2)/t) equates v regul . v regul v ton v ton ramp v oltage pwm outtage turns off mosfet v ton c ramp i ch pwm comparator closed when output low ncp1605, NCP1605A, ncp1605b http://onsemi.com 20 0,00 50,00 100,00 150,00 200,00 250,00 300,00 350,00 02468101214161820 time (ms) vin (v) 0,00 0,50 1,00 1,50 2,00 2,50 3,00 3,50 figure 57. input voltage and on ? time vs time (example with f sw = 100 khz, pin =150 w, v ac = 230 v, l = 200 h) regulation block and low output voltage detection a transconductance error amplifier with access to the inverting input and output is provided. it features a typical transconductance gain of 200 s and a maximum capability of 20 a. the output voltage of the pfc stage is typically scaled down by a resistors divider and monitored by the inverting input (feedback pin ? pin 4). the bias current is minimized (less than 500 na) to allow the use of a high impedance feedback network. the output of the error amplifier is pinned out for external loop compensation (pin 3). t ypically a capacitor in the range of 100 nf, is applied between pin 3 and ground, to set the regulation bandwidth below 20 hz, as need in pfc applications. the swing of the error amplifier output is limited within an accurate range: ? it is forced above a voltage drop (v f ) by some circuitry. ? it is clamped not to exceed 3.0 v + the same v f voltage drop. hence, v pin3 features a 3 v voltage swing. v pin3 is then offset down by (v f ) and divided by three before it connects to the ?v ton processing block? and the pwm section. finally, the output of the regulation is a signal (?v regul ? of the block diagram) that varies between 0 and 1 v. v ref figure 58. regulation block fb off 20 a ovlflag1 2r 3 v 0.955*vref pfcok 200 a r figure 59. correspondence between v control and v regul 1 v 0 v v f v regul v control 3 v + v f v control + + v f v out low detect v f error amplifier v regul + - + - provided the low bandwidth of the regulation loop, sharp variations of the load, may result in excessive over and undershoots. overshoots are limited by the overvoltage protection (see ovp section). to contain the undershoots, an internal comparator monitors the feedback (v pin4 ) and when v pin4 is lower than 95.5% of its nominal value, it connects a 200 a current source to speed ? up the charge of the compensation capacitor (cpin3). finally, it is like if the comparator multiplied the error amplifier gain by 10. one must note that this circuitry for undershoots limitation, is not enabled during the startup sequence of the pfc stage but only once the converter has stabilized (that is when the ncp1605, NCP1605A, ncp1605b http://onsemi.com 21 ?pfcok? signal of the block diagram, is high). this is because, at the beginning of operation, the pin 3 capacitor must charge slowly and gradually for a soft ? startup. remark: as shown in block diagram, the circuitry for undershoots limitation is disabled as long as pin 3 detects standby conditions (v pin3 < 300 mv). this is to suppress the risk of audible noise in standby thanks to the soft?start that softens the bursts. on ? time control for maximum power adjustment as aforementioned, the ncp1605 processes the error amplifier output voltage to form a signal (v ton ) that is used by the pwm section to control the on ? time. (v ton ) compensates the relative weight of the dead ? time sequences measured during the precedent current cycles. during the conduction time of the mosfet, pin 7 sources a current that is proportional to the square of the voltage applied to pin 4 (feedback pin). practically, as pin 4 receives a portion of the output voltage (v out ), i pin7 is proportional to the square of v out . the mosfet turns off when the pin 7 voltage exceeds v ton . hence, the mosfet on ? time (t1) is given by: t 1 c pin7 v ton kv out 2 where k is a constant. the coil current averaged over one switching period is: i coil t i in (t) v in t 1 2l (t 1 t 2 ) t where i in (t) and v in (t) are the instantaneous input current and voltage, respectively, t 2 is the core reset time and t is the switching period. hence, the instantaneous input power is given by the following equation: p in (t) v in (t)i in (t) c pin7 v in 2 2lkv out 2 v ton (t 1 t 2 ) t as aforementioned, we have: v ton (t 1 + t 2 )/t = v regul where v regul is the signal outputted by the regulation block. hence, the average input power is: p in c pin7 v ac 2 2lkv out 2 v regul the maximum value of v regul being 1 v, the maximum power that can be delivered is: p in max c pin7 v ac 2 2lkv out 2 1v to the light of the last equations, one can note that the pfc power capability is inversely proportional to the square of the output voltage. one sees that if the power demand is too high to keep the regulation, (v regul =1v) and the power delivery depends on the output voltage level that stabilizes to the following value: v out c pin7 1v 2lk p out v ac where: ? p out is the output power. ? and is the efficiency. hence, one obtains the follower boost characteristics. the ?follower boost? is an operation mode where the pre ? converter output voltage stab ilizes at a level that varies linearly versus the ac line amplitude. this technique aims at reducing the gap between the output and input voltages to optimize the boost efficiency and minimize the cost of the pfc stage (refer to the mc33260 data sheet for more information, at: http://www.onsemi.com/pub/collateral/mc33260 ? d.pdf ). remark: the timing capacitor applied to pin 7 is discharged and maintained grounded when the drive is low. furthermore, the circuit compares the pin 7 voltage to an internal reference 50 mv and prevents the pwm latch from being set as long as v pin7 is higher than this low threshold. this is to guarantee that the timing capacitor is properly discharged before starting a new cycle. current sense and zero current detection the ncp1605 is designed to monitor a negative voltage proportional to the coil current. practically, a current sense resistor (r cs ) is inserted in the return path to generate a negative voltage proportional to the coil current (v cs ). the circuit uses v cs for two functions: the limitation of the maximum coil current and the detection of the core reset (coil demagnetization). to do so, the circuit incorporates an operational amplifier that sources the current necessary to maintain the cs pin voltage null (refer to figure 60). by inserting a resistor r ocp between the cs pin and r cs , we adjust the cs pin current as follows: [r cs i coil ] [r ocp i pin5 ] v pin5 0 which leads to: i pin5 r cs r ocp i coil in other words, the pin 5 current is proportional to the coil current. i pin5 is utilized as follows: ? if i pin5 exceeds 250 a, an overcurrent is detected and the pwm latch is reset. hence, the maximum coil current is: (i coil )max r ocp r cs 250 a the propagation delay (ipin5 higher than 250 a) to (drive output low) is in the range of 100 ns, typically. ? the pin 5 current is internally copied and sourced by pin 6. place a resistor (r pin6 ) between pin 6 and ground to build a voltage proportional to the coil current. the circuit detects the core reset when v pin6 drops below 100 mv, typically. the pin 6 voltage equating: v pin6 r pin6 r cs r cs i coil , the coil current threshold for zero current detection is: ncp1605, NCP1605A, ncp1605b http://onsemi.com 22 (i coil )zcd r ocp r pin6 r cs 100 mv 100 mv r pin6 250 a (i coil ) max 400 r pin6 (i coil ) max figure 60. current sense block 5 current mirror ics ics emi filter l1 d1 vout m1 icoil icoil drv 10 100 mv ocp (reset of the pwm latch) rzcd 6 r q s ldt zcd outon dt i cs > 250 a ocp vzcd vcc output buffer rdrv the cs block performs the overcurrent protection and the zero current detection. r sense r ocp c in v in v dd cs in v dd cs out - + c bulk load the propagation delay (v pin6 lower than 100 mv) to (drive output high) is in the range of 300 ns, typically. the zero current detection: ? is used to detect the dead ? time sequences (?dt? high) and hence, to process (v ton ) from the error amplifier output (v control ). in other words, this is an input of the on ? time modulation block. ? prevents the mosfet from turning on as long as the ?dt? and ?zcd? signals are low. this is the case as long as some current flows through the coil. this delaying action on the output stage tends to make the mosfet turn on at the valley. to further optimize the valley switching, one can apply the voltage of an auxiliary winding to pin 6 (cs out ). the voltage is compared to an internal 100 mv reference, so that zcd turns high only if (v pin6 < 100 mv). remarks: ? a resistor can be placed between pin 6 and ground to increase the zcd precision. ? it is worth highlighting that the circuit permanently senses the coil current and that it prevents any turn on of the power switch as long as the core is not reset. this feature protects the mosfet from the possible excessive stress it could suffer from, if it was allowed to turn on while a huge current flows through the coil. in particular, this scheme effectively protects the pfc stage during the startup phase when huge in ? rush currents charge the output capacitor. ? in addition this detection method does not require any auxiliary winding. a simple coil can then be used in the pfc stage. it is recommended to: 1. keep r ocp equal to or lower than 5 k 2. choose r zcd as high as possible but not bigger than (3 x r ocp ). this is to avoid that the pin 6 leakage prevents a proper zero current detection. for instance, if r ocp is 2.2 k , r zcd should not exceed 6.6 k . ncp1605, NCP1605A, ncp1605b http://onsemi.com 23 3. place a resistor r drv between the drive pin and pin 6 to ease the circuit detection by creating some over ? riding at the turn on instant. r drv should be selected in the range of 3 times r zcd . for instance, if r zcd is 6.2 k , a 22 k resistor can be used for r drv . overvoltage protection while pfc circuits often use one single pin for both the overvoltage protection (ovp) and the feedback, the ncp1605 dedicates one specific pin for the undervoltage and overvoltage protections. the ncp1605 configuration allows the implementation of two separate feedback networks (see figure 62): ? one for regulation applied to pin 4. ? another one for the ovp function. figure 61. configuration with one feedback network for both ovp and regulation fb hv ovp vout (bulk voltage) figure 62. configuration with two separate feedback networks 1 2 3 4 13 16 14 15 5 6 7 89 12 10 11 r out1 r out3 r out2 fb hv ovp vout (bulk voltage) 1 2 3 4 13 16 14 15 5 6 7 89 12 10 11 r out1 r out2 r ovp1 r ovp2 the double feedback configuration offers some up ? graded safety level as it protects the pfc stage even if there is a failure of one of the two feedback arrangements. however, if wished, one single feedback arrangement is possible as portrayed by figure 61. the regulation and ovp blocks having the same reference voltage, the resistance ratio rout2 over rout3 adjusts the ovp threshold. more specifically, the bulk regulation voltage is: v out r out1 r out2 r out3 r out2 r out3 v ref the ovp level is: v ovp r out1 r out2 r out3 r out2 v ref the ratio ovp level over regulation level is: v ovp v out 1 r out3 r out2 for instance, (v ovp = 105% * v out ) leads to the following constraint: (r out3 = 5% * r out2 ). as soon and as long as the circuit detects that the output voltage exceeds the ovp level, the power switch is turned off to stop the power delivery. remark: like in the ncp1601, the ?v ton processing circuit? is ?informed? when there is an ovp condition, not to over ? dimension v ton in that conditions. otherwise, an ovp sequence would be viewed as a dead ? time phase by the circuit and v ton would inappropriately increase to compensate it (refer to figure 56). pfcok / ref5v signal the ncp1605 can communicate with the downstream converter. the signal ?pfcok/ref5v is high (5 v) when the pfc stage is in normal operation (its output voltage is stabilized at the nominal level) and low otherwise. more specifically, ?pfcok/ref5v? is low: ? during the pfc stage startup, that is, as long as the output voltage has not yet stabilized at the right level. the startup phase is detected by the latch ?l stup ? of the block diagram. ?l stup ? is set during each ?off? phase so that its output (?stup?) is high when the circuit enters an active phase. the latch is reset when the error amplifier stops charging its output capacitor, that is, when the output voltage of the pfc stage has reached its desired regulation level. at that moment, ?stup? falls down to indicate the end of the startup phase. ? in case of a condition preventing the circuit from operating properly, i.e., during the v cc charge by the high voltage startup current source, in a brown ? out case or when one of the following major faults turns off the circuit: ? incorrect feeding of the circuit (?uvlo? high when v cc ncp1605, NCP1605A, ncp1605b http://onsemi.com 25 figure 64. standby management 300 mv 95.5% of the regulation level drive v out l skip v out v pin1 v control remark: ? skip cycle is not allowed du ring the pfc startup phase to avoid that it interferes with the soft ? start. that is why, skip cycle is enabled only when ?pfcok? is high. ? each working phase of the burst mode starts smoothly as pin 3 is grounded at the beginning of it. this soft ? start capability is effective to avoid the audible noise that could possibly result from such a burst operation. ? the circuit leaves the standby mode when the output voltage goes below 95.5% of its regulation level and v pin1 is above 330 mv (300 mv + 30 mv hysteresis). oscillator / synchronization section the oscillator generates the clock signal to set the pwm latch and turn the mosfet on. the oscillator frequency is set by the capacitor that is applied to pin 8. typically, 820 pf force about 60 khz. the maximum allowable oscillator frequency is 250 khz. the clock frequency can also be driven by an external synchronization signal. this block contains two main parts (refer to figure 66): ? the arrangement that consists of charging/discharging current sources, a switch and a comparator. when used in oscillator mode, a capacitor is connected between pin 8 and ground. a current source (100 a) charges the pin 8 capacitor until its voltage exceeds vosch. at that moment, the comparator (?comp_osc?) turns high and activates the discharge current source (200 a). as a consequence, pin 8 actually sinks 100 a that discharge the oscillator capacitor to voscl. at that moment, the comparator turns low and initiates a new charge phase. if the circuit is to be externally triggered, the synchronization signal must cross voscl and vosch to properly turn on and off the ?comp_osc? comparator. also the synchronization signal must be low impedance enough not to be distorted by the pin 8 source and sink currents. ? the ?storing circuitry? that contains a latch and some gates. the raising edge of the ?comp_osc? output sets the ?clock generation? latch to turn high the ?clk? signal. if the timing capacitor of pin 7 is properly discharged (v pin4 <50 mv leading to ?c t ok? high), the pwm block is ready for a new cycle and ?clk? can force the signal ?v set ? in high state. as a consequence, the pwm latch sets. in addition, ?v set ? resets the ?clock generation? latch to make it ready for the next oscillator cycle. the two inverters of figure 66, simply generate some delay to ensure that ?v set ? keeps high long enough to set the pwm latch and reset the ?clock generation? latch (longer delay than that produced by the two gates, may actually be necessary). the oscillator / synchronization block is designed to set the switching frequency. however, the coil current can possibly be non zero at the end of a clock period and the circuit would enter continuous conduction mode (ccm) if the mosfet turned on in that moment. in order to prevent ccm, the ?storing circuitry? of the oscillator / synchronization block, memorizes the ?comp_osc? rising edge (thanks to the ?clock generation? latch) and delays the next mosfet conduction time until the coil current has totally vanished (that is until the signal ?dt? is high ? ?dt? is generated by the current sense block so that it is high during the dead ? time and low otherwise). in other words, crm operation is obtained (refer to figure 65). ncp1605, NCP1605A, ncp1605b http://onsemi.com 26 figure 65. oscillator timing diagram figure 66. oscillator / synchronization block osc/sync dt 100 a 200 a clock generation latch s q r (pwm latch set input) delay (?dt? is high during the dead ? time) comp_osc clk ct_ok discontinuous mode critical mode time clock clock edge set signal inductor current - + v osc h/v osc l figure 67. the current source brings v cc above 15 v and then turns off 15 ma / 0 10 hv hv gnd cvcc auxiliary winding 15 v / 7 v 9 v hvcs_on uvlo (when high, ?uvlo? indicates that the circuit is not properly fed and it sets the fault latch to turn off the circuit) + v cc 9 16 - + + - startup sequence / v cc management at the moment when the pfc stage is plugged to the mains outlet, the internal current source starts charging the v cc capacitor. more generally, the startup current source is enabled whenever v cc drops below v cc stup (7 v, typically). when v cc exceeds the v cc on level (typically 15 v for the ncp1605 and ncp1605b, 10.5 v for the NCP1605A), the current source turns off and the circuit starts pulsing. the energy stored by the v cc capacitor serves to feed the controller and some auxiliary supply must take over before v cc drops below v cc off (9 v, typically), that is, the level below which the circuit stops pulsing. hence, the circuit starts operating when the v cc voltage exceeds v cc on and stops pulsing when v cc drops below v cc off. the hysteresis (6 v for the ncp1605 and ncp1605b, 1.5 v for the NCP1605A) prevents erratic operation as the v cc crosses the v cc on threshold. figure 67 shows the internal arrangement of this structure (the v cc turn on threshold of figure 67 is that of the ncp1605/b). one can note that the startup current source is on during the v cc charging phase and off for the rest of the time. hence, it spends no power during the pfc stage operation and in particular, in light load conditions. that is why the ncp1605 helps meet the most stringent standby requirements. remarks: ? some circuitry (not represented in figure 67) limits the hv pin current to ic2 (below 1 ma) if the v cc voltage is below v cc inhibit. this protects the circuit when the v cc pin is accidentally grounded. the full current capability (around 15 ma) is obtained when v cc exceeds v cc inhibit. ? the circuit is also kept off when the startup current source is on to make a clear distinction between the v cc charge phase and the operating sequence (refer to ?hvcs_on? signal on block diagram). ncp1605, NCP1605A, ncp1605b http://onsemi.com 27 brown ? out detection the brown ? out pin receives a portion of the input voltage (v in ). as v in is a rectified sinusoid, a capacitor must integrate the ac line ripple so that a voltage proportional to the average value of (v in ) is applied to the brown ? out pin. the brown ? out block detects too low input voltage conditions. a hysteresis comparator monitors the pin 2 voltage. before operation, the pfc stage is off and the input bridge acts as a peak detector. hence, the voltage applied to pin 2 is: v pin2 2 vac r bo2 r bo1 r bo2 . after the pfc stage has started operation, the input voltage becomes a rectified sinusoid and the voltage applied to pin 2 is: v pin2 22 vac r bo2 r bo1 r bo2 , i.e., about 64% of the previous value. therefore, the same line magnitude leads to a v pin2 voltage that is 36% lower when the pfc is working than when it is off (refer to figure 69). that is why the ncp1605 features a 50% hysteresis (v bo l = 50% v bo h). when the circuit starts operation, the input voltage equates the ac line peak. hence, the initial threshold of the brown ? out comparator, must be the upper one (v bo = v bo h = 1 v when the ncp1605 leaves the off mode). when a brown ? out condition is detected, the signal ?bo_nok? turns off the circuit (refer to block diagram). bo_nok bo 1 v / 0.5 v emi filter ac line vin figure 68. brown ? out block figure 69. typical input voltage of a pfc stage 400 200 0 v sin 2 vac 2 vac sin( t) r bo2 c bo2 r bo1 r cs c in - + start of pfc operation thermal shutdown (tsd) an internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 150 c typically. the output stage is then enabled once the temperature drops below about 100 c (50 c hysteresis). the temperature shutdown keeps active as long as the circuit is not reset, that is, as long as v cc keeps higher than v cc reset. the reset action forces the tsd threshold to be the upper one (150 c). this ensures that any cold startup will be done with the right tsd level. output drive section the output stage contains a totem pole optimized to minimize the cross conduction current during high frequency operation. the gate drive is kept in a sinking mode whenever the undervoltage lockout is active or more generally whenever the circuit is off (i.e., when the ?fault latch? of the block diagram is high or when the hv current source is on). its high current capability ( ? 500 ma/+800 ma) allows it to effectively drive high gate charge power mosfet. reference section the circuit features an accurate internal reference voltage (v ref ). v ref is optimized to be 3% accurate over the temperature range (the typical value is 2.5 v). v ref is the voltage reference used for the regulation and the overvoltage protection. the circuit also incorporates a precise current reference (i ref ) that allows the overcurrent limitation to feature a 6% accuracy over the temperature range. off mode as previously mentioned, the circuit turns off in the following cases: ? when the high voltage, startup current source charges the v cc capacitor. ? when one of the following major faults is detected: ? incorrect feeding of the circuit (?uvlo? high when v cc ncp1605, NCP1605A, ncp1605b http://onsemi.com 29 remarks: the v control signal does not necessarily reach its clamp level (3.7 v) depending of the load and of the system time constants. in particular, if the circuit starts operation in light load and if the bulk capacitor is not too large, the output voltage v out generally exceeds the regulation level while v control keeps below its upper limit. the output voltage exhibits a 100 or 120 hz ripple (at twice the line frequency). this ripple is also present in the v control voltage even if it is attenuated due to the regulation low bandwidth. like that of v out , this ripple is not represented in figure 70, for the sake of the clarity. figure 70. startup phase in normal conditions v cc v out v control flag1 drive output pfcok circuit state off v cc on v cc off v cc stup v out regulation level v control max = 3.7 v these re ? activations of ?flag1? result from v out 100 or 120 hz ripple (not represented here for the sake of clarity) v cc inhibit ncp1605, NCP1605A, ncp1605b http://onsemi.com 30 figure 71. startup and brown out conditions when the high voltage, startup current source is on, the brown ? out is active and its threshold is the upper one (v bo = v bo h = 1 v). v out regulation level v cc stup v cc off 1 v 0.5 v the circuit is off low consumption v cc on off v cc v out brown ? out pin v oltage drive output circuit state pfcok v cc inhibit fault management block when any of the following faults is detected: brown ? out (?bo_nok?), undervoltage (?uvp?), shutdown (?stdwn?), die overtemperature (?tsd?), the circuit immediately turns off and recovers operation as soon as the fault disappears. in case of uvlo (v cc too low to allow operation), the circuit keeps off until the end of the next v cc charge phase by the hv startup current source. the following block diagram details the function. hvcs_on internal thermal shutdown tsd off uvlo (vcc ncp1605, NCP1605A, ncp1605b http://onsemi.com 32 package dimensions soic ? 16 d suffix case 751b ? 05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch 16 89 8x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ncp1605/d soft ? skip is a trademark of semiconductor components industries, llc (scillc). publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca sales representative |
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